1. Field of the Disclosure
The present disclosure generally relates to electronic devices and, more particularly, to a system and method to reduce current consumption in semiconductor memory chips.
2. Brief Description of Related Art
Memory devices are electronic devices that are widely used in many electronic products and computers to store data. A memory device is a semiconductor electronic device that includes a number of memory cells, each cell storing one bit of data. The data stored in the memory cells can be read during a read operation. FIG. 1 is a simplified block diagram showing a memory chip or memory device 12. The memory chip 12 may be part of a DIMM (dual in-line memory module) or a PCB (printed circuit board) containing many such memory chips (not shown in FIG. 1). The memory chip 12 may include a plurality of pins or ball contacts 24 located outside of chip 12 for electrically connecting the chip 12 to other system devices. Some of those pins 24 may constitute memory address pins or address bus 17, data (DQ) pins or data bus 18, and control pins or control bus 19. It is evident that each of the reference numerals 17–19 designates more than one pin in the corresponding bus. Further, it is understood that the schematic in FIG. 1 is for illustration only. That is, the pin arrangement or configuration in a typical memory chip may not be in the form shown in FIG. 1.
A processor or memory controller (not shown) may communicate with the chip 12 and perform memory read/write operations. The processor and the memory chip 12 may communicate using address signals on the address lines or address bus 17, data signals on the data lines or data bus 18, and control signals (e.g., a row address select (RAS) signal, a column address select (CAS) signal, a chip select (CS) signal, etc. (not shown)) on the control lines or control bus 19. The “width” (i.e., number of pins) of address, data and control buses may differ from one memory configuration to another.
Those of ordinary skill in the art will readily recognize that memory chip 12 of FIG. 1 is simplified to illustrate one embodiment of a memory chip and is not intended to be a detailed illustration of all of the features of a typical memory chip. Numerous peripheral devices or circuits may be typically provided along with the memory chip 12 for writing data to and reading data from the memory cells 26. However, these peripheral devices or circuits are not shown in FIG. 1 for the sake of clarity.
The memory chip 12 may include a plurality of memory cells 26 generally arranged in an array of rows and columns. A row decode circuit 28 and a column decode circuit 30 may select the rows and columns, respectively, in the array in response to decoding an address provided on the address bus 17. Data to/from the memory cells 26 are then transferred over the data bus 18 via sense amplifiers and a data output path (not shown). A memory controller (not shown) may provide relevant control signals (not shown) on the control bus 19 to control data communication to and from the memory chip 12 via an I/O (input/output) circuit 32. The I/O circuit 32 may include a number of data output buffers or output drivers to receive the data bits from the memory cells 26 and provide those data bits or data signals to the corresponding data lines in the data bus 18. The I/O circuit 32 may also include various memory input buffers and control circuits that interact with the row and column decoders 28, 30, respectively, to select the memory cells for data read/write operations.
The memory controller (not shown) may determine the modes of operation of memory chip 12. Some examples of the input signals or control signals (not shown in FIG. 1) on the control bus 19 include an External Clock (CLK) signal, a Chip Select (CS) signal, a Row Address Strobe (RAS) signal, a Column Address Strobe (CAS) signal, a Write Enable (WE) signal, etc. The memory chip 12 communicates to other devices connected thereto via the pins 24 on the chip 12. These pins, as mentioned before, may be connected to appropriate address, data and control lines to carry out data transfer (i.e., data transmission and reception) operations.
FIGS. 2A–2D (collectively referred to hereinafter as “FIG. 2”) depict simplified diagrams illustrating an exemplary prior art timing relationship among the CS, CAS, and RAS signals during a memory read operation. The timing relationship in FIG. 2 is shown with reference to an external clock signal (CLK), which may be supplied to various logic circuits in the memory chip 12 via corresponding clock buffers. However, for the sake of simplicity, the outputs of such clock buffers are also referred to herein as the CLK signals. In the embodiment of FIG. 2, a memory read operation is initiated at time t=t1, i.e., at the rising edge of the second clock pulse in the CLK signal. At the time of memory read operation, the chip select (CS) signal is applied to select one of the memory banks (not shown) in the memory chip 12 from which data is to be read. In the event that there is only one memory bank in the chip 12, the chip select signal may select the memory chip 12 itself. In any event, the CS signal may enable and disable the logic (not shown) in the memory chip 12 that decodes a command (e.g., a READ command, or a WRITE command, etc.) received, for example, from the external memory controller (not shown). As is known in the art, the CAS and RAS signals are also applied relatively simultaneously with the CS signal and in proper combination (e.g., the CAS signal being “low” whereas the RAS signal being “high” for a data read operation) to activate the appropriate row and column(s) in the selected memory bank to read the data bits at the memory address received via the address bus 17. For the sake of simplicity, FIG. 2 does not illustrate an exhaustive set of waveforms present during a memory read/write operation. For example, additional control signals (e.g., a write enable (WE) signal) that are typically operative during a memory read/write operation are not illustrated in FIG. 2 for ease of illustration as may be evident to one skilled in the art.
It is also known in the art that, depending on the design of the memory chip 12, one of the RAS or CAS signals may be used to trigger row activation and precharge operations. For example, in the waveform configuration of FIG. 2, a memory row may remain precharged so long as the RAS signal is “low”, whereas the memory row may be activated for data access once the RAS signal has gone “high” (for example, during a memory read operation as illustrated in FIG. 2). In another configuration, the CAS signal states may be used for similar purpose. Various memory input buffers (not shown) provide the RAS and CAS signals to a control circuit (not shown) to accomplish the row activation and precharge operations. As noted here, all states of the RAS signal (“low” or “high”) (or the CAS signal, as the case may be) are used to accomplish row activation and precharge. Thus, the input buffers (not shown) for the RAS and CAS signals always remains ON to convey the RAS/CAS signal states to the control circuit. The memory address input buffer (not shown) also similarly remains ON to provide the address of the memory location to be accessed during a data read/write operation. In that event, a significant current is consumed by these always ON input buffers. This current consumption may be unnecessary especially when the memory row is in a standby mode after being activated or precharged, i.e., during the time when no data read/write operations are actually taking place.
In one prior art method, the active and precharge standby currents consumed by various memory input buffers may be reduced by deactivating the clock enable (CKE) signal (not shown) supplied to the memory chip 12. In a DDR (Double Data Rate) SDRAM (Synchronous Dynamic Random Access Memory), the CKE signal is generally active at all times that a memory access is in progress, from the issuing of a READ or WRITE command until completion of the data access. However, the DDR SDRAM memory chip (e.g., the memory chip 12) may support a power-down mode in which the CKE signal is de-asserted or deactivated to force various memory circuits, including the memory input buffers (not shown), to enter into an idle state with significantly reduced current consumption. It is observed, however, that the entry into and exit from the power-down mode may require deactivation of the CKE signal for at least three clock cycles or more depending on the design of the memory chip. Furthermore, a valid executable command may not be applied one or more clock cycles after the power-down mode is exited. Such lengthy clock delays may not be desirable in all applications or at all times.
It is therefore desirable to devise a scheme whereby power saving is achieved without forcing the memory chip or a similar electronic device to enter into a power-down mode. In case of a memory chip, it is further desirable to be able to selectively turn on/off various memory input buffers to conserve current consumption, especially active and precharge standby currents.